To increase storage capacity in semiconductor integrated circuit dynamic random access memories (DRAMs), trench capacitors are being widely explored. Nearly all published reports have employed trenches formed in bulk or in regions doped of a given type consistent throughout the wafer. Placing a trench in a well in the opposite type of substrate produces better soft error protection and lower junction leakage (the diffusion component) because the number of minority carriers that are available to discharge the dynamic nodes are only those available within the well dimension which is small compared to the minority carrier diffusion lengths, which are relatively large.
A major problem in placing a trench in a well of the opposite type of conductivity is the fact that only a small amount of charge (due to well doping under the trench) is available to electrically isolate the trench inversion layer or capacitor electrode layer from the substrate.
As an example, consider a p-channel metal-oxide-semiconductor (PMOS) trench capacitor in an n-type well in a p-type substrate as illustrated in FIG. 1. Of course, similar arguments apply for an NMOS trench capacitor in a p-type well in an n-type substrate. In FIG. 1, structures 10 and 12, which may be polysilicon, are plates of trench capacitors having capacitor dielectric layers 11 and 13 and p+ regions 15 and 17, respectively, in n-type well 14 which is adjacent to p-type well 16 in p-type substrate 18. Depletion region 20 forms the lateral punchthrough path between p+ regions 15 and 17.
Envision the p+ regions 15 and 17 of the capacitors 10 and 12 cell potentials at V.sub.DD (e.g. 5 V), the n well 14 at VBB (e.g. +7.5 V) and the p substrate 18 at V.sub.SS (e.g. 0 V). Both the cell to well and well to substrate junctions are reverse biased. The cells 10 and 12 can punchthrough to the substrate 18 if insufficient doping exists in the well 14 below the trenches 10 and 12, that is, between the p+ cell doping region to the p substrate 18. Also, resistance below and between trench capacitors such as 10 and 12 can be very high, thus degrading performance of the circuit.
In addition, for trench capacitors that are placed close to each other, lateral punchthrough currents can exist in depletion region 20 between or below the trench capacitors 10 and 12 where the well doping is light, i.e. where cell to cell depletion regions can touch.
To avoid these problems, two approaches are available. First, a heavily doped n well can be utilized to provide sufficient doping below and between trench capacitors. This approach is not advantageous because the performance of the PMOS device in the heavily doped n well will be compromised.
Alternatively, if a moderately doped well were desired to prevent deleterious effects on PMOS performance, a very deep well is needed to produce sufficient charge below the trench capacitor and between adjacent capacitors. Such a deep well would require long thermal cycles to drive in the well impurity deeply below the trench.
However, for reasonable net charges below the cell electrode (excluding depletion regions) of about 2.times.10.sup.12 ions/cm.sup.2 and reasonable trench depths of 3 microns, for example, a moderately doped well (not lightly doped) would have to be about 8 microns deep, which is unusually deep. Some of the major disadvantages of such deep wells include large lateral diffusion, hence large separations would be required between PMOS and NMOS transistors thus reducing the compactness advantage of the trench technology, and also a thick epitaxial layer would be required to keep the heavily doped substrate from diffusing up into the epitaxial layer. Also, a large transition distance between the lightly doped epitaxial layer and the substrate boundary would be required to prevent degradation of latchup protection due to large vertical up diffusion from the substrate.
These disadvantages conflict with providing latchup immunity with epitaxy, which requires thin epitaxial layers and short transition distances, as well as soft error protection since the deeper well produces a larger volume for minority carrier generation to discharge dynamic nodes. In addition, larger volumes produce more minority carrier diffusion current, which is also deleterious to charge storage in dynamic nodes.